In a typical computer system 100, various types of bus systems, such as a SCSI (Small Computer Systems Interface) bus 102, are used to transfer information between components of the computer system 100, as shown in FIG. 1. A bus adapter typically transfers the information between two different bus systems within the computer system 100. A SCSI host adapter 104, for example, transfers the information between the SCSI bus 102 and a main computer bus 106, such as a PCI (Peripheral Component Interconnect) bus, an ISA (Industry Standard Architecture) bus, etc. Up to fifteen peripheral devices, or SCSI units 108, may be connected to the SCSI host adapter 104 to exchange information with the computer system 100.
When the computer system 100 sends the information to one of the SCSI units 108, a central processing unit (CPU) 110 in the computer system 100 typically forms “bus operation information structures” 112 within a main memory 114 and then instructs the SCSI host adapter 104 to process the bus operation information structures 112. The bus operation information structures 112 include instructions and data with which a sequencer 116 within the SCSI host adapter 104 performs the process (e.g. read data, write data, etc.) requested by the CPU 110. Thus, the SCSI host adapter 104 reads one of the bus operation information structures 112 from the main memory 114, performs the instructions, informs the CPU 110 that the process has been completed and then waits for the CPU 110 to inform it of the next bus operation information structure 112 to be processed.
After the CPU 110 instructs the SCSI host adapter 104 to process a first bus operation information structure 112, the CPU 110 can proceed to build a second bus operation information structure 112 in the main memory 114. However, the CPU 110 must wait for the SCSI host adapter 104 to inform it that the process indicated by the first bus operation information structure 112 has been completed before the CPU 110 can instruct the SCSI host adapter 104 to process the second bus operation information structure 112. A significant amount of time is required for the SCSI host adapter 104 to inform the CPU 110 that the first process has completed and for the CPU 110 to instruct the SCSI host adapter 104 to process the second bus operation information structure 112.
It is with respect to these and other considerations that have given rise to the present invention.